As the end of miniaturization appears to approach for complementary metal-oxide-semiconductor (CMOS) technology, the search for devices to extend computer performance is on. This new technology should be energy efficient, dense, and enable more device function per unit space and time. There have been device proposals, often involving new state variables and communication frameworks.
Tunnel field-effect transistors (TFET) are under intense investigation for low-power applications because of their potential for exhibiting extremely low subthreshold swing (SS) and low off-state leakage. TFET devices are aimed at using supply voltages of less than 0.5 V, enabled by a lower subthreshold swing and do not have the delays associated with positive feedback that are intrinsic to impact ionization, ferroelectricity, and mechanical mechanisms. Further, III-V semiconductors with small effective mass and near broken band alignment are considered to be ideal for TFETs in that they promise high on-current and ION/IOFF ratios. Accordingly, TFETs compete directly with the MOS field-effect transistor (FET) in power, area, and speed, in a commercial temperature range 0° C.-75° C., and in a von Neumann architecture.
TFETs are understood herein to be those types of semiconductor devices that have their source-drain current controlled by an external electric field imposed by a gate. The TFET source-drain current is believed to be brought about by band-to-band tunneling of electrons between adjacent source and drain semiconductors.
FIG. 1 depicts a known TFET 10 that comprises an intrinsic-layer 350 interfacing together a p-doped source-layer 40 and an n-doped drain-layer 50. By aligning the source-layer 40, the intrinsic-layer 350 and the drain-layer 50 along a commonly shared line, i.e., a major axis, the TFET 10 is configured as what is known as a pin TFET 10. The pin TFET 10 also comprises a gate-dielectric 90 and a gate 100 in which the gate-dielectric 90 interfaces together the gate 100 and the source-layer 40. In the pin-TFET configuration, the gate 100 and gate-dielectric 90 are positioned off of the major axis of the TFET by being perpendicular to the commonly shared line defined by the source-layer 40, the intrinsic-layer 350 and the drain-layer 50. As a result of being off-axis the gate 100 imposes an external electric field 310 perpendicular to the internal electric field 300 of the depletion region 320. Also shown is the source-contact 110 and the drain-contact 120 of the TFET 10.
The same reference numerals refer to the same parts throughout the various figures.